WP2 – SiC semiconductor material and devices
Lead Beneficiary | Start month | End month |
---|---|---|
HE | 1 | 40 |
Objectives
- Demonstrate and deliver innovative/state-of-the-art SiC epi wafers with reusable mechanical substrate for 15kV IGBT fabrication;
- Design, fabricate and test SiC high-k IGBTs and diodes rated for 15KV applications;
- Evaluate high-k gate dielectric;
- Evaluate the potential for reduced cost of SiC-based semiconductors, through innovative and improved SiC material and IGBT/MOSFET design (RC-IGBT) and processing
Tasks
Task# | Task name | Task leader | Participants |
---|---|---|---|
2.1 | SiC epi wafers (M1-M36) | II-VI | HE, CSIC |
2.2 | Modeling design and process optimization (M1-M30) | UCAM | CSIC, HE, II-VI |
2.3 | SiC IGBTs, MOSFETs and modules (M9-M40) | HE | CSIC, UCAM, II-VI, DeepC |
Deliverables
Deliverable# | Deliverable name | Lead beneficiary | Type | Due date (in months) |
---|---|---|---|---|
D2.1 | 15kV rated epilayers with high lifetime and low BPD density | II-VI | Demonstrator, pilot, prototype | 40 |
D2.2 | Report on IGBT and RC-IGBT design, and related mask set | UCAM | Document, report | 24 |
D2.3 | 3.3kV MOSFET SiC modules delivery | HE | Demonstrator, pilot, prototype | 24 |
D2.4 | 15kV IGBT dies available for packaging | HE | Demonstrator, pilot, prototype | 31 |
Milestones
Milestone# | Milestone name | Lead beneficiary | Means of verification | Due date (in months) |
---|---|---|---|---|
4 | Splitting method optimize | II-VI | Split Substrate re-use for epi growth | 15 |