WP4 – Validation tests and reliability

Lead Beneficiary Start month End month
UBREMEN 1 48

Objectives

  • Quantify the level to which the developed chips are affected by Gate-instabilities;
  • Detect potential problems regarding the blocking capability of the developed chips;
  • Characterise the issues which might occur during conductions;
  • Measure the limits of the safe operating area regarding switching;
  • Ensure the blocking capability of the packages and of the devices as a whole;
  • Investigate the ins.

Tasks

Task# Task name Task leader Participants
4.1 Gate-Reliability (M1-M36) HE UBremen
4.2 Blocking Capability (Chip Level) (M7-M36) UBremen HE
4.3 Conduction (M12-M36) UBremen HE
4.4 Switching (M24-M48) HE UBremen
4.5 Blocking (Module level) (M24-M48) HE DeepC
4.6 Blocking (Converter Level) (M6-M42) EPFL SuperGrid Institute

Deliverables

Deliverable# Deliverable name Lead beneficiary Type Due date (in months)
D4.1 Report on Partial Discharge test results on converter level UBREMEN Document, report 15
D4.2 Preliminary report on the gate-reliability of the Chips HE Document, report 24
D4.3 Report on the bipolar degradation and its optimum test conditions and on the power cycling capability UBREMEN Document, report 36
D4.4 Preliminary report on the blocking capability UBREMEN Document, report 42
D4.5 Report on reliability of insulation and PD activity of MFT SuperGrid Institute Document, report 42
D4.6 Final report on the reliability of the conventional MOSFET module and the experimental IGBT module including all chip and package topic HE Document, report 48

Milestones

Milestone# Milestone name Lead beneficiary Means of verification Due date (in months)
1 HV SiC switching cell designed and tested UBREMEN Tests results in specs 9
3 Long-term testers upgraded to facilitate the higher voltage UBREMEN Tests up 15kV validated 12